Basic Arithmetic:
We execute the following assembly program on the MIPS simulator.
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.register $s0 -10
.register $s1 5
.register $s2 3
main: add $s3, $s1, $s1 #5+5
add $s4, $s1, $s0 #5+-10
sub $s5, $s1, $s2 #5-3
sub $s6, $s2, $s1 #3-5
and $s7, $s2, $s1 #011 AND 101
exit:
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We will describe the datapath followed by the first add instruction.
Step 1: The first instruction is located in the instruction memory, InstrMemory . The address of the first instruction, PC = 0, is sent to InstrMemory and ALUIncr.
Step 2: The instruction pointed to by PC is sent to the Spliter .
Step 3: The RegWrite flag is asserted by Control . Hence, the result of the addition will be written to the destination register s3.
Step 4: The Spliter splits the instruction into four different parts. The function field of the instruction is sent to ALUControl . The register numbers to be read and the register number to be written are sent to the register file, Registers .
Step 5: ALUcontrol translates the function field into an ALU operation code. For the add operation, the code passed to Main ALU is 010.
Step 6: The register file transmits the two input values, the value of which are stored in the input registers from Step 4, to the ALU.
Step 7: The ALU carries out the addition and sends the result to the register file. The result is stored in the ouput register whose number was determined during Step 4. The zero flag is not set, since the result of the ALU operation, 4 + 4, is non-zero.
Step 8,9: The value of PC is incremented by four in the ALUIncr unit. The program counter now points to the next instruction to be executed.
The datapath of the sub and and operations are similar to the one decribed above. The operation code of the sub operation is 110, while the and operation has operation code 000.
Load/store operations
In order to illustrate the load and store operation, we execute the following assembly code
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.register $s0 -10
.register $s1 4
main: sw $s0, 4($s1) # [8]=-10
lw $s2, 4($s1) # s2=-10
exit:
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The first operation stores the value of s0 at the memory location s1+4 (word aligned). The second operation copies the data stored at s1+4 into s2.
Step 1,2: The first instruction is fetched from instruction memory and sent to the spliter.
Step 3: Register numbers correponding to s0 and s1 are sent to the register file. Both are used as input. The operation opcode is sent to the control unit, Control . The function field of the operation is sent to the ALU control, ALUControl .
Step 4: The control flags corresponding to a store operation are set. Since the value of s0 will be written to a memory location (and not to a register), the MemWrite flag is asserted, while the RegWrite and MemRead flags are deasserted.
Step 5: ALUCtrl passes the operation code for an addition (010) to the ALU. The ALU will add the offset value (4) to the memory address contained in s1.
Step 6,7: The value of s0 (-10) is passed to Memory . This value will be stored at the memory location computed by the ALU (addition). The first operand of the addition, i.e. the value of s1, is passed to the ALU.
Step 8,9: The second operand of the addition is determined by the ALUsrc flag. Since the flag is asserted, the second operand of the ALU is the signed-extended 16-bit offset (4). Otherwise, the second operand would be the second register read from Registers , s1.
Step 10: The destination memory address is computed by the ALU (4+s1=4+4=8).
Step 11,12: The value of s0, -10, is now stored at memory location 8.
Step 13,14,15,16: Finally, the program counter is incremented by 4.
The load operation follows the exact same data path. The only noteworthy difference is the value of the three flags MemWrite , RegWrite and MemRead . Since the value stored at memory location 4+s1 is read and then stored in a register , the control unit asserts MemRead and RegWrite while the MemWrite flag is desasserted.
Branching operations
Let us execute the following assembly code.
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.register $s0 7
.register $s1 7
main: beq $s0, $s1, exit
add $s2, $s1,$s0
exit: sub $s2, $s0, $s1
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The main difference between a regular sub operation and a beq operation is the incrementation of the program counter. For both operations, the zero flag is asserted when the two input registers, s0 and s1, contain the same value. Moreover, for the beq operation, the BranchIn flag is asserted as well. As a consequence, the PCSrc flag, which is the logical and of the zero and the BranchIn flags, is also asserted. The PCSrc flag controls whether the program counter is incremented by 4 ( PCSrc desasserted) or by the 16-bit signed-extended offset contained in the instruction ( PCSrc asserted). Hence, the branch is taken if and only if the value of s0 and s1 are equal.
Jump operation
The jump operation is the simplest one.
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.register $s0 7
.register $s1 7
main: j exit
sub $s2, $s1,$s0
exit:
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The instruction opcode (000010) is passed to the control unit, which then asserts the Jump flag. When the Jump flag is asserted, the program counter is incremented by the 26-bit immediate offset value contained in the instruction (multiplied by 4). Hence, the second assembly line is never executed, since the program counter jumps directly to the location, in instruction memory, pointed to by the exit label.
